1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that is adapted to simplify a control printed circuit board (PCB).
2. Description of the Related Art
A liquid crystal display (LCD) device controls the light transmittance of liquid crystal cells in accordance with a video signal, thereby displaying a picture. An active matrix type LCD device actively controls data by switching data voltages supplied to liquid crystal cells using a thin film transistor (TFT) formed in each liquid crystal cell Clc, as shown in FIG. 1. Accordingly, it is possible to increase the display quality of the image, such as a motion picture, displayed by the LCD device. In FIG. 1, the reference numeral Cst represents a storage capacitor for maintaining the data voltage charged in the liquid crystal cell Clc. A data voltage is supplied to a data line DL, and a scan voltage is supplied to a gate line GL.
As shown in FIG. 2, a related art LCD device includes a control PCB 20, a source PCB 22, a cable 21 connected between the source PCB 22 and the control PCB 20, and a plurality of source COFs (Chips On Film) 24 connected to the source PCB 22 and the LCD panel 25. A source COF 24 is electrically connected to the source PCB 22 and data pads of the LCD panel 25. On the source COF 24 is mounted a data integrated circuit (hereinafter, referred to as “IC”) 23. The control PCB 20 of the LCD device is connected to a system PCB 18 via a wire cable 19.
The system board 18 includes an analog to digital converter, a scaler, and a signal interpolation circuit (not shown). The signal interpolation circuit changes the data supplied through an interface circuit to comply with the resolution of the LCD panel and compensates for the deteriorated video data by the changing the resolution according to a signal interpolation method.
The control PCB 20 is equipped with a control circuit and a data transmitting circuit (not shown). The control PCB 20 supplies the data from the system board 18 via the wire cable 19 to the data ICs 23 of the source PCB 22. Further, it generates the timing control signals for controlling the data ICs 23 and supplies them to the source PCB 22 via the cable 21. Signal lines (not shown) in the source COFs 24 transmit the timing control signals and digital video data from the control PCB 20 to the data ICs 23.
Some of the LCD devices, including for example those made for televisions, have recently been increasing in size. As the LCD panel 25 of the LCD device becomes larger in size, the number of data lines and the number of source COFs 24 increase correspondingly. Moreover, in order to accommodate for more data lines and source COFs, the source PCB 22 becomes larger and more complex. Then, it becomes increasingly difficult to align the source PCB 22 and the source COF 24. Also, as the source PCB 22 becomes larger, it becomes increasingly difficult to couple it to the LCD panel 25 because an automatic mounting device, such as existing SMT (Surface Mount Technology) equipment, is designed on the basis of the source PCB 22 of a relatively small size. Thus, there is a limitation for increasing the size of the source PCB 22 using the existing equipment. Finally, as the LCD device becomes larger, more peripheral components such as memory chips and ICs are required, and the number of required output pins of the control circuit on the control PCB 20 increases. Hence, the cost for manufacturing the control PCB 20 increases.
Moreover, in the related art LCD device configuration as shown in FIG. 2, the control PCB 20 and the system board 18 are manufactured in separate processes. They are coupled through the cable 19, and result in higher manufacturing time and cost. Further, such a configuration has an additional disadvantage in that it tends to make the LCD device thicker.
FIG. 3 shows one potential way to configure large LCD devices. As shown in FIG. 3, the timing controller 131 has dual output ports, and the source PCB is split into two source PCBs 141A and 141B. Each output port of the timing controller 131 is connected to the respective one of the two source PCBs 141A, 141B. However, in this configuration, the timing controller 131 and the control PCB 140 both become larger in size, thereby increasing the cost of the LCD device as well as increasing the overall size of the LCD device for the same size LCD panel.
In the configuration of FIG. 3, the timing controller 131 has two output ports. Then, as shown in FIG. 4, the timing controller 131 includes a left/right data divider 120, a two port expansion part 121 and a data modulator 122. The left/right data divider 120 divides the input digital video data RGB inputted at an input frequency (f) into the left side data RGBl and the right side data RGBr using a frame memory. The data RGBl and RGBr outputted from the left/right data divider 120 are supplied to the two port expansion part 121 at half the input frequency (f/2).
The two port expansion part 121 divides the left/right data RGBl, RGBr inputted at half the frequency (f/2) from the left/right data divider 120 into the odd-numbered pixel data RGBlodd, RGBrodd and the even-numbered pixel data RGBleven, RGBreven. Then, the two port expansion part 121 supplies the data RGBlodd, RGBleven, RGBrodd, and RGBreven to the data modulator 122 at one quarter of the input frequency (f/4).
In the event that the data is modulated by employing the mini LVDS method, the data modulator 122 increases the frequency of the data RGBlodd, RGBrodd, RGBleven, RGBreven from the two port expansion part 121 in accordance with a quadruple speed mini LVDS clock, so as to separately output the left side data RGBlodd, RGBleven and the right side data RGBrodd, RGBreven to two different output ports 141 and 142, respectively, of the timing controller at the same frequency (f) as the input frequency. Each of the left side data RGBlodd, RGBleven and the right side data RGBrodd, RGBreven includes three pairs of odd-numbered pixel data, three pairs of even-numbered pixel data, and a pair of mini clocks. The left side data RGBlodd, RGBleven are transmitted to the first source PCB 141A through the first output port 161 of the timing controller 131, the first connection line 154A and the first FFC (flexible flat cable) 153A. The right side data RGBrodd, RGBreven are transmitted to the second source PCB 141B through the second output port 162 of the timing controller 131, the second connection line 154B and the second FFC 153B. Thus, the number of the output pins of the timing controller 131 needs to be about twice as many as that of a conventional configuration with a single source PCB, causing the timing controller 131 and control PCB 140 to be larger in size and more costly.